This web seminar will illustrate some unique and innovative design-tool technology that enables multiple designers, operating on a LAN or WAN network, to perform simultaneous placement and routing on the PCB. Users of this technology are experiencing more than 60% reduction in layout times.

With the increased requirement of RF design comes a new challenge for PCB Design Engineers: the ability to handle complex copper shapes and import simulator-generated DXF files of RF/Microwave geometries.

PADS recognized this challenge and built a solution into every seat of PADS Layout. PADS customers can now create wireless designs such as cell phones, cell repeater stations, satellite communication, automotive FOBS and any other RF/Microwave application. View this webinar for a first-hand look at the new functionality.

The IBIS Parser, which is created and maintained by the IBIS Committee, will be discussed in detail, as will the IBIS Quality Checklist. The key elements required by the IBIS Quality Checklist will be explored. Common problems with IBIS files will be identified and solutions to these common problems will be discussed, followed by a demonstration. This webinar is part one in a series of webinars focused on IBIS models.

In this one-hour session, we will cover Edge Rate, Parallelism, Trace Spacing, Dielectric Height, Termination, and Guard Traces, as well as their impact on crosstalk. Emphasis will be put on avoiding costly over design - in an attempt to avoid problems that are not fully understood - through proactive pre-layout simulation and planning.

As processor and transmit speeds continue to increase, it becomes increasingly difficult to meet timing and signal integrity requirements for these high speed systems. The HyperLynx DDR2 technology kit provides hardware engineers with the knowledge necessary to quickly develop a DDR2 memory subsystem solution space by investigating ODT (on-die termination) options, analyzing minimum and maximum routing constraints, and making proper flight-time measurements using slew rate derating techniques defined by the JEDEC DDR specification. In this one-hour session, we will discuss the differences between DDR and DDR2 and provide a valuable hands-on demonstration using HyperLynx LineSim.

Common applications include Video, SCSI, Fibre Channel, and Ethernet adaptors, as well as Modems and other bridge applications. The first two generations of PCI were wide parallel interfaces with speeds ranging from 66 to 533 MHz.

PCI Express, the newest generation of PCI, has gone serial, offering a higher level of performance than its predecessors. Along with the performance boost come new and challenging design requirements.

We'll investigate impedance planning for single-ended and differential traces, discussing both analytical solutions and 2D field solutions. Using the HyperLynx Stackup Editor, we'll show how trade-offs can be made between trace width, spacing, and dielectric height to find the right stackup solution for your design while keeping in mind cost and manufacturability.

The steps to creating an IBIS model from lab measurements and SPICE decks will be explored. Learn how to use industry specifications, such as PCI-X and DDR, to create a spec-compliant IBIS model. This webinar is one in a series of webinars focused on IBIS models.