SystemVerilog for FPGA Designers

Select aHands-on Workshop

Location	Date
San Jose, CA	Jun 5, 2008	select

Overview

Modern FPGAs have seen tremendous advances in both performance and capacity. With these increased capabilities, designers are faced with the daunting task of verifying and validating that their design intent is represented in the finished product. SystemVerilog provides a comprehensive language that is a natural extension of Verilog, with the benefits of providing constructs with clearer intent, enumerated types, integrated assertions for simulation and higher language constructs which support design hierarchy and Object Orientated Programming (OOP) styles.

Mentor Graphics' Precision® Synthesis provides the most complete SystemVerilog coverage of this language in FPGA synthesis. This easy-to-use tool empowers designers to utilize sophisticated RTL and physical optimization algorithms to clearly express their design intent.

• Time: 9:00 a.m. - 1:30 p.m.
• 4-hour workshop, 30% presentation / 70% hands-on

Agenda

1. Introduction to effective design with SystemVerilog
2. Learn how to write fewer lines of code that actually do more
3. Mixing Verilog, VHDL and SystemVerilog in the same design

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.

Who Should Attend